Conventional high-capacity memory devices have been enabled by the fabrication of highly dense arrays of conductors and other memory components. In the case of memory devices, higher-capacity storage requires finer conductors and spacing between the conductors, which is typically enabled via photolithographic techniques. As the demand for higher capacity in memory devices increases, however, the need to form even finer features arises.
In an effort to reduce the cost and increase the capacity of memory devices, techniques for storing more than one binary bit in a single memory cell have been developed. The multiple bits are stored as intermediate levels within the cell. In the case of a flash memory cell, a range of voltages may be stored to represent the multiple bit states. In the case of a phase-change memory, a range of resistances may be stored to represent the multiple bit states. Similarly, capacitive memories can store a range of capacitance values. Most types of memory cell may be adapted to store multiple memory states by storing intermediate levels as appropriate for the particular storage cell technology, as known to those of skill in the art. However, one of the problems with multi-bit memory cells is that the range of levels corresponding to the various states may suffer from spreading and ultimately of overlapping levels, which can result in data loss.
In view of the foregoing, there is a need for a memory cell capable of storing two or more discrete bits of data but that enjoys the stability of a single-bit memory cell. Embodiments of the present invention fill this need by stacking two physical memory elements in a single cross-point array bit location, where each of the two stacked elements is set or reset to store information, thereby avoiding the condition where an intermediate level could drift to an adjacent state. Further embodiments allow for intermediate levels to be stored for even more bits stored at a given memory cell location.